Bosch Sensortec and Cadence authors report extending UVM and wreal to analog-centric full-chip verification
A Bosch Sensortec and Cadence DVCon Europe paper reports extending an existing digital UVM verification environment to address analog and full-chip verification in one mixed-signal testbench. The paper describes the architecture and implementation of the reusable approach and explicitly identifies wreal as part of the methodology.
Evidence
A concept for expanding a UVM testbench to the analog-centric toplevel ↗
The 2015 DVCon Europe paper identifies Felix Assmann and Axel Strobel with Bosch Sensortec and Hans Zander with Cadence, and reports a reusable UVM/wreal testbench spanning analog, digital, and full-chip verification.