Bosch Sensortec

Last researched 2026-08-305 indexed events

Public events shown here describe observable source material, not total internal activity.

202620252020–2015

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Jul 24, 2026

Bosch Sensortec posts a PhD role applying agentic AI to ASIC and mixed-signal verification

Bosch Sensortec posted a Dresden PhD role to develop agentic-AI software for accelerating ASIC design, verification, and test. The posting explicitly includes mixed-signal verification and testing and names coverage-driven regression optimization, AMS testbench generation, and closed-loop test-case evaluation and optimization among its example use cases.

Apr 23, 2026

Bosch Sensortec presents SystemC-AMS solver evaluation with MEMS and C2V models

At SystemC Evolution Fika, Alexandra Küster of Bosch Sensortec presented an evaluation of solver efficiency in heterogeneous SystemC-AMS virtual prototypes. The slides compare PRECALC and SEGMENT approaches, adaptive time steps, feedback and discrete-event handling using MEMS and capacitance-to-voltage (C2V) models under repeated-shock conditions. This Event records the 2026 presentation, rather than the first publication of the underlying solver research.

Dec 3, 2025

Bosch Sensortec presents automated setup and maintenance of reusable SystemC-AMS virtual prototypes

Alexandra Küster of Bosch Sensortec presents a COSIDE scripting flow for heterogeneous sensor virtual prototypes combining MEMS, analog, digital and firmware models. The slides contrast manual project copying and backporting with common templates, versioned building blocks, automated updates and a working top-level/testbench scaffold. Python copier, CMake and continuous integration support model reuse and maintenance. Automated test creation remains a next step. This is a reported modeling workflow, not an AI circuit-generation claim.

May 16, 2025

Bosch Sensortec thesis develops a non-ideal SystemVerilog delta-sigma modulator model

Elias Väänänen’s University of Oulu thesis reports work conducted at Robert Bosch Oy within Bosch Sensortec to improve discrete-time delta-sigma modulator design and mixed-signal verification. It develops SystemVerilog and Simulink behavioral models with nonlinearity and noise, selecting an impulse-invariant approach after comparison with EEnet modeling. The work reports simulation studies, but explicitly leaves transistor-level performance matching, including SNDR, and incremental reset operation untested. It therefore does not establish silicon correlation or sign-off accuracy. The date is the repository’s public-availability date, following its May 15 issue date.

2015

Bosch Sensortec and Cadence authors report extending UVM and wreal to analog-centric full-chip verification

A Bosch Sensortec and Cadence DVCon Europe paper reports extending an existing digital UVM verification environment to address analog and full-chip verification in one mixed-signal testbench. The paper describes the architecture and implementation of the reusable approach and explicitly identifies wreal as part of the methodology.