Broadcom authors report a reusable full-chip UVM DMS/AMS methodology
A Broadcom-authored paper reports a full-chip, coverage-driven constrained-random UVM environment for mixed-signal SoCs. It describes selectable analog abstraction through SystemVerilog user-defined nettypes, Verilog-AMS, transistor-level, or mixed views, with interface UVCs, scoreboards, assertions, checkers, and coverage reused across configurations; the authors also report analog-digital and schematic bug findings.
Evidence
Scalable, Re-usable UVM DMS AMS Based Verification Methodology for Mixed-Signal SoCs ↗
2019 DVCon paper by Broadcom authors describing reusable full-chip UVM environments across DMS, AMS, and transistor-level representations.