Broadcom

Last researched 2026-09-216 indexed events

Public events shown here describe observable source material, not total internal activity.

20262020–2011

JavaScript is required for Timeline filtering. Every Event remains available in the chronological Events view.

Sep 8, 2026

Broadcom storage-ASIC postings call for cross-site DMS methodology and AI-assisted verification automation

A Broadcom Senior Digital / Mixed-Signal IC Design or Verification Engineer posting for Data Center Enterprise Storage, indexed as posted September 8, 2026 under requisition R026970, describes a methodology leader and technical bridge across US and Asia design centers. Its verification scope includes UVM-based block- and system-level testbenches, functional and code coverage closure, SVA and UVM/OVM methodology, event-driven analog-boundary modeling, and AI-assisted workflows for testbench generation and debug. A separate Broadcom careers posting, R025692, describes a closely related DMS verification methodology-leader role with the same cross-site and AI-assisted-automation themes; the postings do not establish that the two requisitions belong to the same team or define a company-wide standard.

Jul 7, 2026

Broadcom lists DMS modeling for touch, wireless-power, health-sensing, and satellite analog front ends

Broadcom posted an Analog/Mixed Signal Verilog Modeling Design Engineer role for touch-controller, wireless-power, health-sensing, and satellite analog front ends. The description calls for SystemVerilog DMS models, UDT/UDR nettypes including wreal or EEnet, model-versus-schematic verification, and experience using Cursor or chipAgents to generate analog SystemVerilog models and testbenches.

Jun 30, 2026

Broadcom clocking-design role calls for MSV and RNM strategies in PLL, FLL, and DLL verification

Broadcom posted a Digital Mixed-Signal Lead role for the digital control infrastructure of PLL, FLL, and DLL clocking subsystems. The description assigns partnership with verification teams to drive mixed-signal-verification and real-number-modeling strategies for high-coverage loop simulations and also names full-chip CDC and RDC sign-off for the clocking network. This is evidence of a public hiring mandate, not proof that the listed verification strategies were already deployed across Broadcom.

2026

Broadcom presents a unified AMS-SDF approach for high-capacity macro verification

Synopsys AMS SIG India 2026 lists a Broadcom user presentation by Jeevan Ramaswamy titled “High-Capacity Macro Verification: A Unified AMS-SDF Approach using VCS PrimeSim AMS.” The public agenda and proceedings establish a Broadcom-authored macro-verification flow combining AMS and SDF in VCS PrimeSim AMS. Because the presentation deck is gated, this Event does not assert implementation details, capacity results, speedup, or deployment scope beyond the published title.

2019

Broadcom authors report a reusable full-chip UVM DMS/AMS methodology

A Broadcom-authored paper reports a full-chip, coverage-driven constrained-random UVM environment for mixed-signal SoCs. It describes selectable analog abstraction through SystemVerilog user-defined nettypes, Verilog-AMS, transistor-level, or mixed views, with interface UVCs, scoreboards, assertions, checkers, and coverage reused across configurations; the authors also report analog-digital and schematic bug findings.

2011 – 2012

LSI and Cadence records describe RNM verification of a hard-disk-drive preamplifier

A 2011 DVCon paper by LSI and Cadence authors describes real-number models for mixed-signal verification of a hard-disk-drive preamplifier and reports roughly 24x speedup over the referenced SPICE simulation with about 0.3% gain inaccuracy. A later Cadence-authored report describes LSI applying the models in mixed-signal SoC verification, reporting roughly 600x speedup, 95% accuracy, full functional coverage, and no functional bugs in first silicon. These performance and outcome statements retain their respective paper and vendor-report modalities.