Broadcom lists DMS modeling for touch, wireless-power, health-sensing, and satellite analog front ends
Broadcom posted an Analog/Mixed Signal Verilog Modeling Design Engineer role for touch-controller, wireless-power, health-sensing, and satellite analog front ends. The description calls for SystemVerilog DMS models, UDT/UDR nettypes including wreal or EEnet, model-versus-schematic verification, and experience using Cursor or chipAgents to generate analog SystemVerilog models and testbenches.
Evidence
Analog/Mixed Signal Verilog Modeling Design Engineer ↗
Official Broadcom role dated July 7, 2026, for product-scoped DMS modeling, nettypes, schematic correlation, and AI-assisted generation experience.