Dialog Semiconductor author reports production chip-level analog regressions

A 2020 CadenceLIVE paper by Dialog Semiconductor's Yi Wang describes a programmable Verilog-AMS testbench with SystemVerilog Assertions and an asynchronous state machine for chip-level analog regressions. The paper reports more than 30 scenarios and 156 runs completing in 9.5 hours for daily signoff; Cadence's conference repository says the simulated results were subsequently supported by silicon measurements.