Dialog Semiconductor and Cadence report a unified RTL, DMS, and AMS testbench flow
At CadenceLIVE Europe 2020, Dialog Semiconductor's Peter Grove described work with Cadence R&D on a unified testbench and an LRM-compliant SystemVerilog netlister spanning RTL, digital mixed-signal, and analog/mixed-signal simulation. This is a dated Dialog Semiconductor record and does not imply methodology transfer to Grove's later affiliations.
Evidence
CadenceLIVE Europe 2020 Proceedings ↗
Cadence's conference repository lists Peter Grove of Dialog Semiconductor and the unified RTL, DMS, and AMS testbench presentation.
A Mixed-Signal Universal Testbench for RTL/DMS/AMS (UTB) ↗
Grove's later technical article describes the unified testbench, Cadence R&D collaboration, SystemVerilog netlister, and common RTL/DMS/AMS flow.