IBM authors publish HRL-Topo for LLM-guided hierarchical analog circuit topology synthesis

IBM Research lists HRL-Topo by Prashanth Vijayaraghavan, Xin Zhang and coauthors as a DAC 2026 publication dated July 26. The work combines language-model circuit guidance with hierarchical reinforcement learning to construct analog circuit topologies and evaluate them through simulation. This records a topology-synthesis research publication, rather than fixed-topology sizing alone or deployment across IBM design teams. The date is IBM's publication-record date, not a separately verified presentation time.