IBM

Last researched 2026-08-304 indexed events

Public events shown here describe observable source material, not total internal activity.

20262020–2013

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Oct 6, 2026

HRL advertises cryogenic-CMOS model correlation and UVM-AMS verification leadership

HRL Laboratories' Qubit Systems Laboratory posted an AMS verification role for quantum-control cryogenic CMOS. It assigns Verilog-A/AMS, wreal and SV-RNM models aligned with transistor-level implementations; UVM-AMS environments, SVA/PSL and coverage; regression infrastructure; and block-to-top-level integration for ADCs, DACs, PLLs, LDOs, SerDes and power-management blocks. Model correlation spans PVT/corner simulation and later measurements. The employer identifies HRL as an IBM company. These are advertised responsibilities, not demonstrated model accuracy.

Jul 26, 2026

IBM authors publish HRL-Topo for LLM-guided hierarchical analog circuit topology synthesis

IBM Research lists HRL-Topo by Prashanth Vijayaraghavan, Xin Zhang and coauthors as a DAC 2026 publication dated July 26. The work combines language-model circuit guidance with hierarchical reinforcement learning to construct analog circuit topologies and evaluate them through simulation. This records a topology-synthesis research publication, rather than fixed-topology sizing alone or deployment across IBM design teams. The date is IBM's publication-record date, not a separately verified presentation time.

Jul 15, 2026

IBM and Duke researchers publish EXPLORE for language-model-guided analog topology exploration

Guanglei Zhou, Xin Zhang and coauthors publish EXPLORE, combining an autoregressive circuit language model with Monte Carlo tree search and simulation feedback to explore analog circuit topologies. The manuscript lists Duke University, MIT-IBM Watson AI Lab and IBM Research affiliations. It concerns generating circuit structure as well as optimizing candidate designs. July 15 is the initial arXiv publication date; later MLCAD presentation is supporting context for the same research, not evidence of production adoption.

2013

IBM and Cadence authors report wreal modeling and digital mixed-signal regressions on an IBM project

A DVCon 2013 paper by IBM and Cadence authors reports that IBM created and deployed Verilog-AMS wreal models on a mixed-signal project. The authors describe correlation against circuit-level simulations, approximately 40x simulation speedup for a representative case, and digital mixed-signal regressions that could run overnight.