Infineon links mixed-signal constrained-random tests to XVP across simulation, PXI and ATE

An Infineon-authored paper described linking Markov-based mixed-signal constrained-random test generation to an Executable Verification Plan (XVP) so test cases could be transferred to Cadence simulators and MATLAB/Simulink for simulation and to PXI and ATE for post-silicon verification. The paper also reports applying generated tests on mixed VHDL-AMS/Verilog models and post-silicon PXI/ATE systems and identifying mixed-signal design issues.