Infineon

Last researched 2026-10-1523 indexed events

Public events shown here describe observable source material, not total internal activity.

20262025202420212020–2009

Infineon

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Oct 5, 2026

Infineon seeks a Senior Staff engineer for AI-based SV-RNM and automotive AMS verification

Infineon's Bengaluru Senior Staff Engineer Analog Mixed-Signal Verification posting assigns AI-based SystemVerilog real-number behavioral models with speed/accuracy tradeoffs for pre-silicon verification. The role leads automotive subsystem and analog-on-top full-chip verification, develops AMS plans, SPICE-netlist integration, checkers, assertions and coverage, and models bandgaps, LDOs and buck-boost regulators. This is an advertised development and methodology-leadership mandate; the posting does not disclose an AI algorithm, model-generation results or production adoption.

Sep 9, 2026

Infineon lists internships and graduate roles for AMS model verification

Infineon posted Graduate - Analog Mixed-Signal Design Verification Engineer role HRC1763746 with an official September 9, 2026 date. It assigns Verilog-AMS/SystemVerilog model generation and maintenance, testbenches, nominal/corner simulation, fault injection and regressions. Related Andover and Shanghai internships observed October 5 cover behavioral models, AMS IP/SoC environments, RTL/model integration and model-quality checks. January/summer 2027 are planned employment starts. The official graduate date is the earliest verified publication among these grouped roles; the internships' first publication dates remain unconfirmed. These are hiring requirements, not deployed practices.

Sep 3, 2026

Infineon graduate role pairs analog behavioral modeling with AI verification methodology

Infineon advertised an Andover Regional Graduate Program – Engineer Verification and Validation role for computing power-management products, with a retained September 3 listing. It assigns AI-based verification-flow improvement for coverage and documentation, alongside Verilog-AMS/SystemVerilog behavioral models, schematic correlation, targeted testbenches and analog/digital integration debug. The AI duty is an assigned methodology task; the posting does not say that AI generates those models. This is distinct from the later general AMS internship advertisements.

Sep 3, 2026

Infineon posts a SystemVerilog/svreal modeling role for FPGA and firmware validation

Infineon posted a Bengaluru Staff Engineer Design role whose description calls for developing RNM with SystemVerilog and svreal, building FPGA prototypes for SoC and system validation, and supporting pre- and post-silicon firmware validation and hardware/software debug. The role also covers simulation and FPGA automation, continuous integration, and modeling and prototyping methodology.

Jul 2, 2026

Infineon keynote describes generative-AI real-number-model creation within an AI-based verification methodology

A SMACD 2026 keynote by an Infineon principal engineer describes industrial experience connecting AI assistants, retrieval-augmented knowledge systems, and EDA tools through APIs, along with a current focus on an AI-based verification methodology. Its concrete example generates SystemVerilog real-number models from schematics, specifications, or other source models while emphasizing domain knowledge, guardrails, compliance, and human review. This Event records the scope described by the keynote, not a measured deployment result.

Jun 4, 2026

Doctoral thesis reports SystemC-AMS virtual testing for gate-driver test hardware

Davide Turossi reported defending his doctoral thesis at the University of Milano-Bicocca on June 4, 2026 and explicitly thanked Infineon for hosting and supporting the research. The university abstract describes a SystemC-AMS/COSIDE framework modeling automatic test equipment, devices under test and probe-card circuitry. Its gate-driver cases address over-current protection and output peak-current measurement, comparing virtual test solutions with measurements on manufactured hardware. This records the thesis and acknowledged research support, not company-wide adoption.

May 2026

Infineon retargets IEEE P1687.2 test descriptions into SystemVerilog UVM for automotive smart-power shift-left

An Infineon Automotive Power paper at ETS 2026 describes retargeting IJTAG/IEEE P1687.2 test-case descriptions through a renderer and a pin-level time-stamp/value transport such as STIL into top-level SystemVerilog UVM testbenches for pre-silicon functional verification of automotive smart-power devices. Its SoC DUT combines digital RTL with analog behavioral models, while UVM-compatible agents apply external analog and supply stimuli. The paper illustrates replay of a measured noisy supply waveform and shows a charge-pump voltage (VDD CP) response to supply interruptions followed by an SPI diagnostic readout. These are paper-reported verification results, not measured silicon performance or evidence of wider adoption.

Dec 3, 2025

Infineon presents mixed RF and SystemC-AMS models for isolated gate-driver integration verification

Guillermo Conde of Infineon presents SystemC-AMS/COSIDE models for smart gate drivers using coreless-transformer isolation. The flow combines discrete-event, timed-data-flow and electrical models with selectable RF baseband/passband abstractions. The integration example connects the RF isolation path to SPICE-level surrounding circuits for AMS verification. December 3 is the scheduled presentation date; November 27 on internal slide footers is not treated as the public presentation date. The slides describe a modeling approach, not company-wide deployment.

Sep 11, 2025

Infineon authors present AI-based mixed-signal modeling with SystemVerilog RNM

The official DVCon India 2025 agenda lists an Infineon presentation titled 'Scalable and cost-effective mixed signal modelling using AI with SV-RNM' by Sathyanarayana Ramamoorthy, Rutvikkumar Patel, Anand Rahul, Kranthi Kiran, and Hareesh Perumal. The public agenda establishes the presentation and its stated topic; without a retained paper, this Event does not assert a specific model-generation method, result, or deployment scope.

Dec 1, 2024

Infineon role targets centralized automation of analog and mixed-signal verification

An Infineon job record for its central design-flow department in Dresden describes developing and integrating methods and software extensions for analog and mixed-signal verification automation, including SPICE simulation, reliability, optimization, and regression tooling. The role also lists AI/ML knowledge as an advantage. This is evidence of a public hiring mandate, not proof that a specific automated or AI-assisted flow was already deployed.

Nov 15, 2024

Infineon verification role lists SV-RNM behavioral modeling and AMS verification for SoCs and IP

An Infineon job record for a Senior Engineer Verification role lists Verilog, wreal, or SV-RNM behavioral modeling; AMS verification for SoCs or IPs; test planning and debug; and independent mixed-signal-verification project and methodology-improvement responsibilities. It also names Verilog-AMS, SystemVerilog/UVM, and Cadence, Synopsys, and Mentor AMS tools. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.

2024

Infineon authors extend svreal checks and FPGA debug for fixed-point mixed-signal models

A DVCon Europe paper by Vishal Chovatiya, Gabriel Rutsch, and Wolfgang Ecker describes svreal extensions that detect range violations and precision loss in simulation by comparing fixed-point calculations with a shadow SystemVerilog real representation. Its Integrated Fixedpoint Analyzer interprets fixed-point signal values during FPGA debug. A buck-converter model illustrates the flow between host simulation and FPGA emulation.

Aug 4, 2021

Stanford and Infineon authors publish an open-source framework for mixed-signal FPGA emulation

Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, and Mark Horowitz published a framework combining msdsl model generation, svreal synthesizable fixed- and floating-point representations, and anasymod FPGA build and control automation. The paper demonstrates a DragonPHY receiver, a firmware-controlled flyback converter, and an NFC-powered chip. Stanford dates publication to August 4, 2021; the TCAD journal issue is dated July 2022.

2020

Infineon and Stanford authors report FPGA prototypes for mixed-signal magnetic sensors

A DVCon Europe paper led by Gabriel Rutsch reports two FPGA prototypes for automotive magnetic sensors, using msdsl to generate synthesizable analog functional models and anasymod for FPGA build and control. One prototype supports real-time hardware-in-the-loop and customer integration; the other accelerates regression testing. The paper describes their use across product definition, verification, and design-in.

Jul 15, 2019

Infineon case study runs the same test program on virtual and physical ATE before first silicon

A JKU/Infineon paper presented a virtual ATE flow that executes production-style test programs against a SystemC/SystemC-AMS virtual DUT before first silicon. In an Infineon ASIC case study, the same test program was run on the virtual ATE and later on a Teradyne UltraFLEX system, exposing the same register-test error; the authors report that this enabled test-program checks months earlier than the conventional flow.

Oct 24, 2018

NXP and Infineon present UVM mixed-signal practices and standardization needs

At DVCon Europe 2018, NXP and Infineon presented company practices for extending UVM into mixed-signal verification. NXP described analog/mixed-signal verification-component and UVC concepts and identified a need for flexible APIs between physical and signal layers, including a common interface for third-party VIP; Infineon presented its A-UVM analog extension with real-valued transactions, constrained-random stimulus, automated analog checks, waveform comparison, functional coverage, and an IGBT gate-driver application. The tutorial explicitly asked whether an Accellera UVM-AMS working group should be created, and Accellera later stated that DVCon Europe discussions resulted in creation of the proposed working group.

2018

Infineon authors report automated generation and validation of real-number models and UVM-MS testbenches

A DVCon 2018 paper by Infineon authors describes a meta-model-driven flow that automatically generates real-number models and UVM-MS testbench components. In its mixed-signal ADC case, the generated RNM ran in 4.5 seconds versus 74.1 seconds for the referenced VHDL model, and the generated testbench exposed a deadlock in the analog implementation.

2016

Infineon author reports UVM-based AMS verification of automotive mixed-signal requirements

A DVCon 2016 paper by Infineon's Silvia Strähle describes UVM-based verification of an automotive mixed-signal design with more than 1,000 requirements. The environment could exchange a VHDL behavioral model for a transistor-level netlist where needed and checked analog quantities and operating conditions including temperature, overcurrent, and overtemperature behavior.

May 13, 2015

Infineon and FH Technikum Wien publish a common pre/post-silicon test description for mixed-signal SoCs

A joint FH Technikum Wien/Infineon Technologies Austria paper presented a bidirectional pre/post-silicon bridge for Infineon's mixed-signal verification flow. It used a common platform-independent human-readable scripting test description, implemented with Perl, while environment-specific interpreters mapped the same test intent into the AGENtiX SystemC simulation environment or the JAZZ/lab-instrument post-silicon environment.

2014

Infineon authors report Analog UVM stimulus and automated behavioral-model comparison

Two Infineon DVCon 2014 papers describe an Analog UVM library for constrained-random analog transactions and automated comparison of analog behaviors. The model-validation flow uses an earth mover's distance implementation connected through SystemVerilog and C to convert waveform comparison into regression pass/fail results, reducing reliance on manual waveform inspection.

2014

Infineon and Mentor authors report UPF-based power-aware mixed-signal verification of a sensor SoC

A DVCon 2014 paper by Infineon and Mentor Graphics authors reports applying UPF with RTL and SPICE content to power-aware mixed-signal verification of a tire-pressure-monitoring sensor SoC. The paper says the flow exposed power blackouts, sequencing errors, missing level shifters, and incorrect isolation polarity before gate-level verification.

Sep 22, 2011

Infineon links mixed-signal constrained-random tests to XVP across simulation, PXI and ATE

An Infineon-authored paper described linking Markov-based mixed-signal constrained-random test generation to an Executable Verification Plan (XVP) so test cases could be transferred to Cadence simulators and MATLAB/Simulink for simulation and to PXI and ATE for post-silicon verification. The paper also reports applying generated tests on mixed VHDL-AMS/Verilog models and post-silicon PXI/ATE systems and identifying mixed-signal design issues.

Jul 2009

Infineon and University of Trieste authors report Verilog HDL buck-converter modeling

A PRIME-09 paper by University of Trieste researchers and Infineon Technologies authors Giuseppe Bernacchia and Emanuele Bodano, affiliated with Padova, describes a discrete-time buck-converter model implemented in Verilog HDL. The model combines the switching network, output inductor and capacitor, including parasitic effects. The authors compare simulated electrical waveforms with an experimental prototype in PWM continuous-conduction, discontinuous-conduction and pulse-frequency-modulation modes, and investigate controller behavior during mode transitions.