Infineon authors report automated generation and validation of real-number models and UVM-MS testbenches
A DVCon 2018 paper by Infineon authors describes a meta-model-driven flow that automatically generates real-number models and UVM-MS testbench components. In its mixed-signal ADC case, the generated RNM ran in 4.5 seconds versus 74.1 seconds for the referenced VHDL model, and the generated testbench exposed a deadlock in the analog implementation.
Evidence
Methodology for Automated Generation and Validation of Analog Behavioral Models for Mixed-Signal Verification ↗
DVCon's record identifies the Infineon work on automated RNM and UVM-MS generation and validation.
Methodology for Automated Generation and Validation of Analog Behavioral Models — paper ↗
The paper details the meta-model flow, reported MADC simulation timings, and analog-implementation deadlock found by the generated testbench.