Infineon case study runs the same test program on virtual and physical ATE before first silicon
A JKU/Infineon paper presented a virtual ATE flow that executes production-style test programs against a SystemC/SystemC-AMS virtual DUT before first silicon. In an Infineon ASIC case study, the same test program was run on the virtual ATE and later on a Teradyne UltraFLEX system, exposing the same register-test error; the authors report that this enabled test-program checks months earlier than the conventional flow.
Evidence
Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows ↗
Full paper describing a SystemC/SystemC-AMS virtual ATE methodology and an Infineon ASIC case using the same test program on virtual and Teradyne UltraFLEX targets.
Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows ↗
TUM publication record for the ISVLSI 2019 paper and conference dates.