Infineon verification role lists SV-RNM behavioral modeling and AMS verification for SoCs and IP

An Infineon job record for a Senior Engineer Verification role lists Verilog, wreal, or SV-RNM behavioral modeling; AMS verification for SoCs or IPs; test planning and debug; and independent mixed-signal-verification project and methodology-improvement responsibilities. It also names Verilog-AMS, SystemVerilog/UVM, and Cadence, Synopsys, and Mentor AMS tools. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.