Infineon applies IEEE P1687.2 chip-level PDL to post-silicon smart-power lab verification

An Infineon ITC 2024 poster described an industrial application of IEEE P1687.2 for post-silicon verification of a smart-power device. The work used IJTAG chip-level PDL to simplify test implementation in the laboratory and framed the approach as a way to improve reuse where lab flows had limited reuse of test cases and patterns from pre-silicon verification or test engineering.