Infineon graduate role pairs analog behavioral modeling with AI verification methodology
Infineon advertised an Andover Regional Graduate Program – Engineer Verification and Validation role for computing power-management products, with a retained September 3 listing. It assigns AI-based verification-flow improvement for coverage and documentation, alongside Verilog-AMS/SystemVerilog behavioral models, schematic correlation, targeted testbenches and analog/digital integration debug. The AI duty is an assigned methodology task; the posting does not say that AI generates those models. This is distinct from the later general AMS internship advertisements.
Evidence
Infineon: Regional Graduate Program – Engineer Verification and Validation — employer LinkedIn posting ↗
Employer-attributed duties explicitly pair an AI verification-methodology assignment with analog behavioral modeling, Verilog-AMS/SystemVerilog and schematic correlation. Current LinkedIn JobPosting metadata gives October 7 UTC, a later channel posting than the retained September record.
Hardware FYI: retained Infineon graduate verification role ↗
Retained full description displays September 3, 2026 and the same role/location/duties. This secondary date is used rather than treating the later LinkedIn posting as the first occurrence.