Infineon retargets IEEE P1687.2 test descriptions into SystemVerilog UVM for automotive smart-power shift-left

An Infineon Automotive Power paper at ETS 2026 describes retargeting IJTAG/IEEE P1687.2 test-case descriptions through a renderer and a pin-level time-stamp/value transport such as STIL into top-level SystemVerilog UVM testbenches for pre-silicon functional verification of automotive smart-power devices. Its SoC DUT combines digital RTL with analog behavioral models, while UVM-compatible agents apply external analog and supply stimuli. The paper illustrates replay of a measured noisy supply waveform and shows a charge-pump voltage (VDD CP) response to supply interruptions followed by an SPI diagnostic readout. These are paper-reported verification results, not measured silicon performance or evidence of wider adoption.