InnoPhase and Designer's Guide authors report Python-generated UVM testbench infrastructure for AMS designs
A DVCon U.S. 2024 paper by InnoPhase and Designer's Guide Consulting authors reports a Python and Jinja flow that generates UVM testbench infrastructure from a DUT port list, including analog interfaces and agents plus register-abstraction integration. The paper presents deterministic template-based automation; it does not describe an AI-generated testbench flow.
Evidence
UVM Testbench Automation for AMS Designs ↗
The official proceedings record identifies J. B. David with InnoPhase, Henry Chang with Designer's Guide Consulting, and the March 6, 2024 presentation.
UVM Testbench Automation for AMS Designs — paper ↗
The paper describes Python/Jinja generation from DUT ports, including analog interfaces, agents, and register-abstraction infrastructure.