Microchip author introduces an Analog Information Model abstraction for SystemVerilog RNM

A Microchip-authored paper introduces an Analog Information Model that separates real-number model functionality from the SystemVerilog mechanism used to transport analog information. The proposed nodes and connectors provide a common interface across user-defined nets, UPF-based nets, and wreal, allowing stimulus and checking components to be reused while the underlying transport representation changes.