Microchip

Last researched 2026-09-258 indexed events

Public events shown here describe observable source material, not total internal activity.

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Jul 29, 2026

Microchip and Siemens authors report selective-SPICE digital-top verification with RTL and UPF

A Microchip and Siemens DAC 2026 presentation reports a digital-on-top mixed-signal flow combining selected SPICE blocks with RTL and UPF power intent. The presentation describes AI-accelerated Solido analysis and reports more than 22× acceleration for the presented case. This preserves the customer/vendor presentation modality and does not imply the result applies to every Microchip design.

Jul 28, 2026

Microchip and Siemens report full-chip AMS verification for FPGA I/O PVT calibration

At DAC 2026, Microchip and Siemens authors described full-chip analog mixed-signal verification of FPGA I/O PVT calibration spanning distributed I/O banks. The presented calibration combines a SAR-based digital block with analog circuitry that manages reference currents and voltages. The authors report that Siemens Symphony Pro reduced simulation time by about 3x and memory usage by about 2-3x while supporting regression across multiple I/O standards and extreme PVT conditions; these are presentation-reported results for the described case.

Jun 14, 2026

Microchip lists system-level AMS verification across full-chip and chiplet boundaries

Microchip posted a Technical Staff Engineer role for system-level AMS verification and power and signal integrity on SoCs and chiplet platforms. The description covers subsystem, full-chip, and cross-chiplet AMS and SPICE simulation, mature-node analog integrated with advanced-node digital, multi-voltage domains, methodology development, silicon bring-up, and simulation-to-silicon correlation.

Jan 13, 2026

Microchip AIM patent grant describes SystemVerilog classes for analog information

The US12524593B2 grant publication names Charles McClish as inventor and Microchip Technology as assignee. It describes Analog Information Model (AIM) SystemVerilog classes carrying analog properties such as voltage, current and resistance, with connected model instances exchanging and resolving information. This Event dates the grant publication, separate from the earlier AIM paper; it does not establish that AIM was first invented or newly deployed in 2026.

2026

Microchip job posting combines full-chip mixed-signal verification with LLM-assisted debug and test work

Microchip’s Senior Engineer I – Verification posting R1497-26 describes full-chip SoC/mixed-signal verification with SystemVerilog/UVM, analog-IP interactions and coverage closure, plus LLM-assisted code/stimulus generation, root-cause analysis, log/waveform triage and failure clustering. A November 4 Senior Engineer II role R4346-26 names the Chennai WIPD group and adds Verilog-A/AMS and SV-RNM models, SPICE and applicable silicon correlation for ADCs/DACs, PLLs, LDOs, bandgaps and clocking circuits, alongside AI-assisted verification, modeling and debug methodology. The related mandates are grouped without assuming a shared team or completed AI deployment; the later posting does not change this Event’s original year-only date.

Nov 7, 2025

Siemens reports Microchip AMS coverage and checkpoint-debug case studies

A Siemens forum recap reports two Microchip posters: mixed-signal code-coverage analysis of a temperature/voltage sensor exposed RTL bugs missed by standalone digital verification; a battery-backed SRAM case used Symphony Get Analog Value and checkpoint save/restore for analog visibility and debug. The date records publication of the vendor recap.

2023

Microchip author introduces an Analog Information Model abstraction for SystemVerilog RNM

A Microchip-authored paper introduces an Analog Information Model that separates real-number model functionality from the SystemVerilog mechanism used to transport analog information. The proposed nodes and connectors provide a common interface across user-defined nets, UPF-based nets, and wreal, allowing stimulus and checking components to be reused while the underlying transport representation changes.

2021

Microchip author reports reusable UVM agents for UDN and UPF analog stimulus

A Microchip-authored paper reports bidirectional UVM agents for SystemVerilog user-defined nettypes and UPF supply-net pins. The agents generate static and time-varying analog stimulus, monitor values, and are configured through reusable objects; the paper reports using the approach with the three largest simulators and discusses portability differences among them.