Microchip job posting combines full-chip mixed-signal verification with LLM-assisted debug and test work

Microchip’s Senior Engineer I – Verification posting R1497-26 describes full-chip SoC/mixed-signal verification with SystemVerilog/UVM, analog-IP interactions and coverage closure, plus LLM-assisted code/stimulus generation, root-cause analysis, log/waveform triage and failure clustering. A November 4 Senior Engineer II role R4346-26 names the Chennai WIPD group and adds Verilog-A/AMS and SV-RNM models, SPICE and applicable silicon correlation for ADCs/DACs, PLLs, LDOs, bandgaps and clocking circuits, alongside AI-assisted verification, modeling and debug methodology. The related mandates are grouped without assuming a shared team or completed AI deployment; the later posting does not change this Event’s original year-only date.