Micron clock-architecture internship combines HBM clock exploration with AI-assisted analysis

Micron advertised Richardson internship JR110765 in its HBM Architecture team, with a retained listing dated September 14. The role evaluates clock distribution, WDQS timing, PLL concepts, jitter, noise sensitivity and IO timing margins, compares alternative clock architectures and supports architecture-level decisions. It assigns LLM/GenAI engineering workflows for analysis and data evaluation, and links AI assistance to design exploration. This is an advertised analysis mandate, not proof of AI topology synthesis or HDL model generation.