Micron

Last researched 2026-10-156 indexed events

Public events shown here describe observable source material, not total internal activity.

2026

JavaScript is required for Timeline filtering. Every Event remains available in the chronological Events view.

Oct 5, 2026

Micron advertises full-chip AMS verification with AI-agent development and output evaluation

Micron advertised October 5 LinkedIn role JR113919 for block-to-full-chip AMS verification, power-loss/brownout checks and agents for requirements-to-test extraction, triage, failure clustering, waveform guidance and coverage gaps. Related official JR114263, dated October 8, adds behavioral/schematic models accurate enough for each verification objective. Both require validated engineering data, human review and evaluation of AI-output usefulness and limitations. Preferred experience measures reduced manual effort, faster debug, traceability or verification completeness; these are evaluation criteria, not reported improvements. The distinct requisitions are grouped as an advertised development mandate.

Sep 30, 2026

Micron NAND analog-design role assigns AI agents to circuit review and specification checks

Micron posted Hyderabad Staff Engineer, Analog Design role JR113578 for NAND Flash circuits including charge pumps, regulators, ADCs/DACs, references and sensor interfaces. It assigns development and evaluation of AI agents for specification-to-check extraction, schematic or connectivity review, and verification debug. Reusable workflows connect engineering data, scripts, simulation outputs and design checks, with validation and human review before decisions. These pre-silicon review tasks extend beyond the separate layout-automation and simulation-orchestration duties; the posting does not establish AI-generated circuit topology or achieved deployment benefits.

Sep 14, 2026

Micron clock-architecture internship combines HBM clock exploration with AI-assisted analysis

Micron advertised Richardson internship JR110765 in its HBM Architecture team, with a retained listing dated September 14. The role evaluates clock distribution, WDQS timing, PLL concepts, jitter, noise sensitivity and IO timing margins, compares alternative clock architectures and supports architecture-level decisions. It assigns LLM/GenAI engineering workflows for analysis and data evaluation, and links AI assistance to design exploration. This is an advertised analysis mandate, not proof of AI topology synthesis or HDL model generation.

Jul 2026

Micron HBM verification architect role assigns GenAI methods and pre-silicon AI debug

Micron advertised HBM Staff Design Verification Engineer/Architect role JR94769 in Richardson. It assigns GenAI verification-methodology development aligned with HBM design cycles and AI-assisted root-cause analysis of pre-silicon as well as post-silicon issues. The role accepts digital, FastSPICE analog or mixed-signal co-simulation/real-number-modeling experience and spans IP/SoC verification architecture. Its scope is broader than dedicated AMS verification; it does not assign every GenAI task to RNM. A retained July listing predates the current September Workday date.

Jun 30, 2026

Micron posts UVM-AMS and RNM verification role for DDR and ONFI PHY

Micron posted a Staff Engineer role for a high-speed DDR and ONFI PHY team whose description calls for reusable SystemVerilog/UVM environments with mixed-signal simulators and fast behavioral models using SystemVerilog EEnet or wreal, or Verilog-AMS, in place of SPICE subcircuits. It also covers full-chip gate-level, power-aware, and mixed-signal co-simulation plus model validation. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.

Mar 4, 2026

Micron job posting combines full-chip AMS verification with AI-assisted coding

A Micron careers posting for an AMS verification role describes full-chip analog, digital, and firmware interaction, behavioral models, power-cycle verification, and use of AI-assisted coding to automate design and analysis work. This is evidence of the capabilities requested in a public hiring mandate, not proof that a specific AI-assisted flow was already deployed or measured.