Micron posts UVM-AMS and RNM verification role for DDR and ONFI PHY

Micron posted a Staff Engineer role for a high-speed DDR and ONFI PHY team whose description calls for reusable SystemVerilog/UVM environments with mixed-signal simulators and fast behavioral models using SystemVerilog EEnet or wreal, or Verilog-AMS, in place of SPICE subcircuits. It also covers full-chip gate-level, power-aware, and mixed-signal co-simulation plus model validation. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.