MPS student listing assigns chip-top AMS verification and RNM, wreal and schematic models

An Arizona State University recruiting listing dated June 11 advertised an MPS Analog Mixed Signal Verification Intern role in San Jose for a 20–24 week Summer/Fall 2026 placement. The employer description assigns chip-top verification planning and AMS simulation for full-custom precision analog signal-chain ASICs, behavioral models ranging from RNM and logical models to Verilog-AMS electrical/wreal and schematic models, register and trim-mode debug with analog schematics and post-layout RTL, and regression and infrastructure support. June 11 is the university listing's recruitment date; the listed application deadline was June 19.