NVIDIA Taiwan recruitment describes SystemVerilog modeling within its high-speed I/O SerDes group

A public NVIDIA recruiting post by Yvonne Chen advertised a Taiwan Senior Mixed-Signal Design Engineer role in the high-speed I/O SerDes group. The role works with analog designers on SystemVerilog models of closed-loop PLLs, receive CTLEs, SAR ADCs and optical components, and with system architects and digital designers on architecture specifications and adaptation algorithms. The post also assigns reusable scripting and silicon bring-up work. It establishes a recruiting mandate, not deployed modeling results; the recruiter is not identified as a technical team lead.