NVIDIA

Last researched 2026-09-024 indexed events

Public events shown here describe observable source material, not total internal activity.

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Aug 14, 2026

NVIDIA posts a mixed-signal cell modeling and verification role

On August 14, 2026, NVIDIA posted a role to develop behavioral models and verification environments for custom mixed-signal cells used across NVIDIA products. The listing names Verilog, SystemVerilog, Perl, and Python, and covers cells including PLLs and high-speed interconnects, emulation and prototyping, and library- and chip-level integration.

Jul 27, 2026

NVIDIA job posting seeks agentic-AI workflows for custom-IP verification

An NVIDIA Senior ASIC Design Verification Engineer posting for its Circuit Solutions Group describes custom IP spanning clocking, voltage regulation, and silicon correlation. It asks the role to help develop and deploy agentic-AI frameworks for stimulus generation, regression triage, debug, and root-cause analysis, while listing real-number modeling of low-level digital or mixed-signal designs and VCS-XA co-simulation as differentiating experience. This is evidence of a public hiring mandate, not proof of the capability or measured effect of a completed framework.

Nov 24, 2025

NVIDIA and university authors publish HeaRT for hierarchy-aware AMS circuit design exploration

Souradip Poddar, Chia-Tung Ho and coauthors present HeaRT, an agentic AMS design framework that organizes circuit hierarchy, functional roles and feedback relationships to guide design changes. The work includes topology exploration as well as parameter refinement. The authors list NVIDIA, UT Austin and George Washington University affiliations. This records a research publication, not NVIDIA production deployment. The Event retains the November 24, 2025 initial-publication date; the March 26, 2026 revision is supporting evidence for the same research milestone.

Feb 1, 2024

NVIDIA Taiwan recruitment describes SystemVerilog modeling within its high-speed I/O SerDes group

A public NVIDIA recruiting post by Yvonne Chen advertised a Taiwan Senior Mixed-Signal Design Engineer role in the high-speed I/O SerDes group. The role works with analog designers on SystemVerilog models of closed-loop PLLs, receive CTLEs, SAR ADCs and optical components, and with system architects and digital designers on architecture specifications and adaptation algorithms. The post also assigns reusable scripting and silicon bring-up work. It establishes a recruiting mandate, not deployed modeling results; the recruiter is not identified as a technical team lead.