NXP recruits for a Catania MCU team and related AMS verification roles
Jim Caravella posted a public invitation to join the first phase of a new MCU team using analog/mixed-signal IP, sharing NXP’s Catania MCX recruitment. A related Junior Mixed-Signal Verification Engineer posting assigns SystemVerilog RNM and Verilog-AMS analog models, verification coverage, robustness, test modes and DFT in new full-product teams. An October 2 Catania internship separately names an AMS Verification Team and proposes behavioral models, assertions, debug and coverage; its direct membership in the MCX team is not established. These sources record team-building and hiring, not completed technology deployment or NXP’s first presence in Catania.
Evidence
Jim Caravella: Catania MCU team recruitment ↗
Original post metadata gives January 22, 2026 at 06:55:11 UTC. The post describes first-phase MCU/AMS-IP team building and shares NXP MCX/Catania recruitment. It does not establish Caravella’s formal title.
NXP Careers: Junior Mixed-Signal Verification Engineer (R-10063614)
Reviewed official recruiting text describes Catania MCU team-building and SV-RNM/Verilog-AMS model assignments. Its first posting date is unconfirmed; a later direct endpoint check returned HTTP 403. It does not change the January recruiting-post date.
NXP Careers: Catania AMS verification internship (R-10064672) ↗
Official public Workday startDate is October 2, 2026. The full description names the AMS Verification Team and proposed modeling, assertions, debug and coverage duties, but specifies neither an HDL nor a direct MCX-team affiliation.