NXP

Last researched 2026-10-1519 indexed events

Public events shown here describe observable source material, not total internal activity.

2026202520242020–2010

Infineon

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Sep 23, 2026

NXP lists an AI-agent internship for migrating behavioral models and generating validation testbenches

NXP posted Toulouse internship R-10066989 on September 23 for AI-agent behavioral-model migration and mixed-signal stimuli/testbench generation, using Verilog/SystemVerilog and Verilog-AMS. Evaluation covers code quality, test-scenario coverage, automation rate, time savings and robustness, with regression checks and documented limitations. October 5 role R-10067009 covers AI-generated HDL AMS models and an oscillator/ADC/supply Golden Library. Related October 6 Design Enablement role R-10067212 assigns Python agents, LLM/RAG and surrogate-model generation, verification and qualification; its model language is unspecified. These grouped research advertisements propose evaluation work rather than demonstrate successful deployment.

Sep 23, 2026

NXP lists an internship to generate mixed-signal VIP and assertions from specifications using AI agents

On September 23, NXP listed a Toulouse internship to prototype and evaluate AI-assisted verification-component generation for digitally controlled mixed-signal IP, particularly DC/DC converters. The project analyzes specifications for interfaces, control sequences and faults, generates reusable SystemVerilog/UVM components and coverage, and proposes assertions for protocols, timing, forbidden states and fault responses. Generated components are to be integrated and tested on representative examples, with robustness and limitations evaluated.

Sep 22, 2026

NXP lists a 2027 NFC power-management internship combining wreal, SVA, formal proof and AI exploration

On September 22, NXP listed a six-month internship starting in the first quarter of 2027 within its Sophia Antipolis Secure Transactions and Identification verification team. The project concerns NFC SoC power management, including power gating, reset, clocking and wreal analog representations. It assigns SystemVerilog test scenarios, SVA, coverage analysis and Jasper formal property verification, alongside investigation of AI/ML approaches for analog and mixed-signal verification. The AI work is exploratory.

Apr 23, 2026

NXP-affiliated Accellera chair reports SystemC-AMS revision and regression-test progress

Martin Barnasconi, identified with NXP and as Accellera SystemC Technical Committee chair, presented the SystemC-AMS standardization status at SystemC Evolution Fika. The slides report preparation for the next IEEE 1666.1 revision and work toward a public regression-test repository. Accellera coordinates this standardization work; it is not an NXP product release. The presentation does not announce a newly issued standard or the first public regression suite: a 2023 presentation already links a regression-test tar archive.

Feb 7, 2026

NXP co-op listing assigns AMS and digital integration, wreal views, simulation and silicon bring-up

A Discover Technata recruiting listing dated February 7 advertised an NXP Analog Mixed-Signal Design Co-Op for early-career engineers. The role supports analog/digital integration, schematic and netlist views, connectivity checks, Verilog-AMS and wreal view generation, simple RTL wrappers and digital-on-top build checks. It also assigns block- and top-level Spectre/Xcelium/AMS Designer simulations, testbench and model packaging work, and automated lab measurements including power-up sequences. The listing is no longer accepting applications; its date is the recruiting board's posting date.

Jan 22, 2026

NXP recruits for a Catania MCU team and related AMS verification roles

Jim Caravella posted a public invitation to join the first phase of a new MCU team using analog/mixed-signal IP, sharing NXP’s Catania MCX recruitment. A related Junior Mixed-Signal Verification Engineer posting assigns SystemVerilog RNM and Verilog-AMS analog models, verification coverage, robustness, test modes and DFT in new full-product teams. An October 2 Catania internship separately names an AMS Verification Team and proposes behavioral models, assertions, debug and coverage; its direct membership in the MCX team is not established. These sources record team-building and hiring, not completed technology deployment or NXP’s first presence in Catania.

2026

NXP job posting seeks an AMS verification leader for its Milan advanced-power team

An NXP Careers posting for a Senior AMS Verification leader in Milan describes ownership of verification strategies, plans, environments, regressions, coverage, behavioural models, checkers, assertions, and reusable components for the Advanced Power System team, including top-level mixed-signal verification and methodology improvement. The requested experience includes Verilog, SystemVerilog, UVM, SVA, Verilog-AMS, SystemC, WREAL/RNM, and mixed-signal EDA tools. This is evidence of a public hiring mandate, not proof that every listed method is already deployed. A related Chandler PMIC leadership listing checked on October 5 adds explicit power-sequencing and fault-management checks using reusable AMS/UVM/RNM environments.

2026

NXP seeks end-to-end AMS verification ownership for high-speed SerDes IP

NXP posted a Principal AMS Verification Engineer role to own SerDes verification from concept through sign-off. The description covers UVM and UVM-AMS environments, RNM and Verilog-AMS model development and validation, PLL and CDR behavior, link training and adaptation, jitter and noise analysis, assertions and coverage, PVT and stress verification, and correlation among MATLAB or Python, behavioral models, and transistor-level simulation. This is evidence of a hiring mandate, not proof of project completion.

Dec 4, 2025

Carna Zivkovic presents NXP-related SystemC-AMS UWB verification and process-variation modeling

Carna Zivkovic presents a SystemC/SystemC-AMS model of a UWB transmitter, channel and receiver, comparing behavior with MATLAB and hardware measurements and examining how receiver gain/noise variations affect packet errors and sensitivity. The cover identifies her as an external contractor, not an NXP employee appointment. The slides credit Shrief Rizkalla as the main author of earlier work and Zivkovic as presenter. This Event records the December presentation and its statistical-model extension, not first publication of the underlying UWB research.

Oct 15, 2025

NXP authors preserve shared block variations in a SystemC-AMS PLL performance model

NXP and RPTU authors presented variation-aware PLL performance evaluation at DVCon Europe 2025. Public slides integrate statistical performance kernels into SystemC-AMS charge-pump and loop-filter models, preserving 23 shared variations between the blocks. They evaluate PLL lock-time distributions across 2,000 runs and compare approaches with independently modeled block distributions. Related NXP work appeared in 2023; this event records the 2025 evaluation rather than the methodology's first introduction.

Oct 15, 2025

NXP authors report UVM-MS modeling and verification of an automotive gyroscope

An NXP DVCon Europe 2025 paper reports a gyroscope verification flow using UVM-MS, custom user-defined nets for voltage, current, resistance, and capacitance, Python through DPI, and safety-mechanism checks. In one capacitor-model comparison, the paper reports 24 seconds for a custom enet implementation, 129 seconds for EEnet, and 256 seconds for Verilog-AMS. Those timings apply only to that example and simulator setup.

Feb 4, 2025

Accellera releases UVM-MS 1.0 with participation from seven tracked companies

On February 4, 2025, Accellera released UVM-MS 1.0, defining mixed-signal bridge and proxy components for driving and monitoring mixed-signal nets. The standard's participant list names active contributors from Cadence, Intel, Siemens EDA, Synopsys, NXP, Qualcomm, and Renesas; participation in the standard does not by itself establish deployment at those companies.

Mar 4, 2024

Accellera releases Verilog-AMS 2023 under working-group chair Peter Grove of Renesas

Accellera approved Verilog-AMS 2023 for release on March 4, 2024. The update enhances analog constructs and adds compiler directives intended to support UVM-MS. Peter Grove of Renesas chaired the working group, and the standard's participant list names contributors affiliated with Analog Devices, Cadence, NXP, Qualcomm, Renesas, Siemens EDA, Synopsys, and Texas Instruments. Participation does not by itself establish company deployment.

2024

NXP authors report reusing AMS verification tests in post-silicon validation

An NXP-authored paper reports reusing pre-silicon AMS functional tests in post-silicon validation with matching stimulus timing and side-by-side waveform visualization. The methodology uses Jupyter and Python around a reusable environment for product variants; the authors report deployment across multiple projects and products and one-day silicon bring-up.

Oct 24, 2018

NXP and Infineon present UVM mixed-signal practices and standardization needs

At DVCon Europe 2018, NXP and Infineon presented company practices for extending UVM into mixed-signal verification. NXP described analog/mixed-signal verification-component and UVC concepts and identified a need for flexible APIs between physical and signal layers, including a common interface for third-party VIP; Infineon presented its A-UVM analog extension with real-valued transactions, constrained-random stimulus, automated analog checks, waveform comparison, functional coverage, and an IGBT gate-driver application. The tutorial explicitly asked whether an Accellera UVM-AMS working group should be created, and Accellera later stated that DVCon Europe discussions resulted in creation of the proposed working group.

2018

NXP authors extend one UVM environment across the digital and analog sides of an automotive Ethernet PHY

An NXP-authored paper reports verifying an IEEE 802.3bw 100BASE-T1 PHY with one UVM environment extended to handle its analog interface. The environment adds analog source and probe components, error injection, and analog-domain coverage while retaining the digital UVM register-model environment; the authors demonstrate the approach on a released automotive Ethernet PHY.

2016

NXP authors report low-power full-chip verification across Verilog, wreal, and Verilog-AMS abstractions

An NXP-authored paper reports low-power mixed-signal IoT case studies using CPF power intent, assertions, formal and connectivity checks, and self-checking verification while moving a verification database through Verilog, wreal, and Verilog-AMS abstraction levels. The examples include PMU, brownout detector, and LDO behavior at full-chip scope. The paper identifies evaluating UVM as a next step rather than reporting UVM deployment.

2011

Freescale coauthor proposes realtime regular expressions for analog and mixed-signal assertions

At FMCAD 2011, John Havlicek and Freescale Semiconductor's Scott Little presented syntax and semantics for realtime regular expressions that extend SystemVerilog Assertion-style regular expressions to describe continuous-time analog and mixed-signal properties. The paper says the work was influenced by the Accellera analog-assertions effort; it does not claim an internal Freescale deployment.

2010

Freescale author reports generating mixed-signal abstraction models from circuit-simulation traces

A 2010 journal paper coauthored by Freescale Semiconductor's Scott Little proposes automatically generating abstraction models from transistor-level simulation traces for formal verification and system simulation. The paper demonstrates the approach on a switched-capacitor integrator and a PLL phase detector and evaluates how the generated models reproduce the observed circuit behaviors.