onsemi Treo role calls for reusable digital-on-top verification of analog power and clock IP

onsemi posted a Mixed-Signal Verification Engineer role for analog IP integrated into digital-on-top SoCs on its 65 nm Treo BCD platform. The position owns SystemVerilog and UVM testbenches, real-number and Verilog-A/AMS behavioral models for PLLs, LDOs, DC-DC converters, and oscillators, executable plans, assertions, coverage and checkers, regression debug, and model-validation strategies. This is evidence of a public hiring mandate, not proof of completed verification outcomes.