Qualcomm, Advantest and Cadence demonstrate PSS handoff from design verification to silicon validation

At DVCon U.S. 2025, Qualcomm, Advantest and Cadence presented a unified device-sign-off flow that hands PSS-based tests from design verification to a silicon-validation bench through an FDAT functional-test container. The concrete use case used a parameterized CPU-binning test, native binary execution, runtime parameters and PSS coverage/debug; the presenters reported a 5x PSS productivity gain and hours saved per DV-SV iteration by avoiding pattern conversion.