Qualcomm

Last researched 2026-09-285 indexed events

Public events shown here describe observable source material, not total internal activity.

202620252024

Texas Instruments

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Nov 7, 2026

Observed Qualcomm Toronto internship offers possible SV modeling and AMS validation assignments

As observed November 7, Qualcomm advertised a Toronto Analog Design internship for 12 or 16 months beginning in May or June 2027. Possible assignments include SystemVerilog analog behavioral models, AMS co-simulation to validate them, simulation-data peer review and testbench-performance metrics, with analog, digital, firmware and system teams. The application feeds multiple project-specific roles, so these are possible duties rather than completed work or a promise that every intern receives the same assignment. The Event uses the observation date because a reliable first-publication date is unconfirmed; 2027 is the planned placement year.

Oct 7, 2026

Qualcomm-affiliated authors publish RFChipAgent for LNA topology selection, schematic assembly and verification

Awani Khodkumbhe and Qualcomm-affiliated coauthors publish RFChipAgent, a human-supervised LLM-agent flow for analog/RF design. It connects document retrieval, topology selection, schematic and testbench assembly, simulation-guided optimization, and operating-point and stability checks. The reported case is a GF22FDSOI 60 GHz wideband LNA. The paper is a preprint submitted for possible publication, not a product release, measured-silicon result or evidence of company-wide adoption. Khodkumbhe also lists UC Berkeley affiliation.

Sep 2026

Qualcomm lists Staff SerDes role spanning behavioral modeling, system verification, and silicon correlation

Qualcomm Canada ULC listed a Cross-Functional Engineer, Staff role for high-speed SerDes work. The description assigns oversight of analog and mixed-signal behavioral-model development and verification, higher-abstraction analog verification, system verification with digital-verification and firmware teams, calibration, power modeling, and correlation of pre-silicon models and predicted power with post-silicon measurements. It asks for 106 Gbps-and-higher SerDes experience and SystemVerilog behavioral modeling, and names clock generation and distribution, VCOs, phase interpolators, PLLs, ADCs, and DACs among relevant circuit experience.

Feb 4, 2025

Accellera releases UVM-MS 1.0 with participation from seven tracked companies

On February 4, 2025, Accellera released UVM-MS 1.0, defining mixed-signal bridge and proxy components for driving and monitoring mixed-signal nets. The standard's participant list names active contributors from Cadence, Intel, Siemens EDA, Synopsys, NXP, Qualcomm, and Renesas; participation in the standard does not by itself establish deployment at those companies.

Mar 4, 2024

Accellera releases Verilog-AMS 2023 under working-group chair Peter Grove of Renesas

Accellera approved Verilog-AMS 2023 for release on March 4, 2024. The update enhances analog constructs and adds compiler directives intended to support UVM-MS. Peter Grove of Renesas chaired the working group, and the standard's participant list names contributors affiliated with Analog Devices, Cadence, NXP, Qualcomm, Renesas, Siemens EDA, Synopsys, and Texas Instruments. Participation does not by itself establish company deployment.