Renesas presents SystemVerilog UDN RNM techniques for power and switched-capacitor models

Two Renesas-authored papers presented in one DVCon Europe session report SystemVerilog UDN techniques for real-number modeling. One says Renesas had used Voltage-Current-Resistance UDNs for current-limited LDOs, smart chargers, and DCDC converters, then introduces a Voltage-Charge-Capacitance form for a switched-capacitor crystal oscillator and reports a 90,000x simulation-speed boost benefiting block design and chip-level integration verification. The companion paper models an LDO with current limiting and load capacitance using a self-triggering VIR-UDN mechanism and reports 84x fewer events for similar behavior, or about 778x at a coarser voltage step.