Renesas role combines top-down AMS verification with CAD and flow automation for full-custom ASICs

Renesas posted a senior staff AMS verification role to support top-down design and full-custom ASIC verification. The position covers Verilog-AMS and SystemVerilog behavioral models, real-number modeling, self-checking mixed-signal simulation, verification planning and regressions, chip-level integration, and Python and Cadence SKILL automation for project and verification flows. This is evidence of a public hiring mandate, not proof that every listed method was deployed across Renesas.