Renesas posts senior verification roles for automotive PMIC RNM/AMS environments
Renesas posted related Senior Principal roles for Automotive PMIC verification, covering RNM/AMS model integration, RTL-to-GLS correlation, PVT analysis, switched-mode regulators/LDOs, cross-team handoffs and methodology leadership. The Chandler role also assigns evaluation of emerging verification technologies and AI-based solutions. A related Staff description requires PMIC RNM/AMS environment architecture and Verilog/SystemVerilog proficiency. These grouped requirements include exploratory AI evaluation, not proof of AI-generated models, deployed tools or measured benefits; the original August 19 Event date is retained.
Evidence
Senior Principal Verification Engineer — Chandler ↗
Official Renesas requisition 20032032_2026-08-19 for Automotive PMIC verification leadership, RNM/AMS environment architecture, GLS correlation, PVT, ATE/Silicon Validation handoffs, mentoring, and methodology improvement. Rechecked October 15: the methodology responsibility explicitly includes evaluating emerging verification technologies and AI-based solutions; this is exploratory evaluation rather than a disclosed deployment.
Senior Principal Design Verification Engineer — Plano ↗
Official Renesas requisition 20032030_2026-08-19 repeats the Automotive PMIC RNM/AMS and cross-domain verification mandate and states that the role drives verification strategy across multiple product platforms.
Renesas Careers: Staff Verification Engineer ↗
The official public posting describes automotive PMIC RNM/AMS model integration and Verilog/SystemVerilog proficiency. It currently links to posting 744000152788539; requisition/reposting metadata is not substituted for the existing Event’s date.