Samsung authors report SystemVerilog RNM verification of an SSD power-management IC
A DVCon Europe 2022 paper by Samsung authors describes SystemVerilog real-number modeling for verification of a complex SSD power-management IC. The flow combined 25 models, randomized I2C programming, Python-based register checks, and 68 tests; the authors report a six-week implementation effort and simulation speedups of 100x to 1,000x over the referenced schematic simulations.
Evidence
Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex SSD PMIC ↗
DVCon's record identifies the Samsung SSD PMIC real-number-modeling case study.
Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex SSD PMIC — paper ↗
The paper documents the RNM models, randomized I2C and Python checks, test count, effort, and reported speed range.