Samsung

Last researched 2026-08-3110 indexed events

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Aug 20, 2026

Samsung job posting seeks AMS verification for converter, LDO, and PMIC designs

A Samsung careers posting in Bengaluru seeks an AMS verification engineer to create behavioral real-number models for converters and LDOs and work on PMIC verification using UVM, assertions, and automation. This is evidence of a public hiring mandate and its requested scope, not proof that every listed technique was already deployed on a shipped design.

Feb 25, 2025

Samsung authors report configurable AFE/channel models for PCIe receiver-logic verification

Samsung authors present a configurable analog front-end behavioral and channel model in a UVM testbench for 16.0-GT/s PCIe receiver digital logic. Randomizable offsets and FIR channel coefficients exercise eye monitoring, offset calibration, DFE adaptation and margin logic, including deliberately out-of-range conditions that expose retry and timeout bugs. For the reported regression, time to 100% digital code coverage falls from 54.26 to 16.13 hours. The conventional comparison uses an XMODEL analog behavioral model; this does not establish Scientific Analog coauthorship or collaboration. The authors retain conventional circuit-reflecting models for verification requiring actual AFE/channel behavior.

Jun 24, 2024

Samsung authors present SystemVerilog EEnet models for PMIC loading verification

At DAC 2024, Samsung authors presented a digital mixed-signal verification approach that combines lower-level behavioral models with a SystemVerilog user-defined EEnet to represent electrical loading in power-management IC verification. The presentation describes extending the DMS verification checklist to performance and loading behaviors beyond voltage-only interfaces.

2024

Samsung authors report reusing a UVM environment with SPICE for display-PMIC AMS verification

A DVCon Europe 2024 paper by Samsung authors describes reusing a configurable digital mixed-signal UVM environment for a selected set of analog/mixed-signal tests coupled to a SPICE simulator. In the display-PMIC case, the authors report finding critical schematic issues before tapeout and correlating verification results with silicon measurements.

2024

Samsung Foundry authors add write-time and write-voltage variation to an MRAM SystemVerilog model

Samsung Foundry authors report a SystemVerilog embedded-MRAM behavior model that incorporates write-time and write-voltage variation into bit-cell test behavior. The reported simulations exercise random write time and voltage-dependent intended write failures, and the authors state that the variation-aware operation was verified with the Digital Nonvolatile-memory Assist IP used to control the MRAM for IP validation.

2023

Samsung authors report UVM-based mixed-signal verification of an OLED display PMIC

A DVCon Europe 2023 paper by Samsung authors reports a UVM-based mixed-signal verification environment for an OLED display power-management IC. The authors describe 45 validated wreal models, 142 tests, assertions and automated checks, a fifteen-week turnaround, resolution of multiple port-direction issues, and pin-connectivity checks designed to guard against mismatches.

2022

Samsung Foundry authors report symbolic mixed-signal verification for embedded nonvolatile memories

Samsung Foundry authors report a mixed-signal IP verification method using netlist extraction, module conversion, custom testbenches, and Synopsys ESP symbolic simulation. The paper applies the method to eMRAM, eFLASH, and OTP memories to compare behavioral simulation models with schematic-derived implementations and describes the flow as extending symbolic verification to mixed-signal memory structures not natively covered by the tool.

2022

Samsung authors report SystemVerilog RNM verification of an SSD power-management IC

A DVCon Europe 2022 paper by Samsung authors describes SystemVerilog real-number modeling for verification of a complex SSD power-management IC. The flow combined 25 models, randomized I2C programming, Python-based register checks, and 68 tests; the authors report a six-week implementation effort and simulation speedups of 100x to 1,000x over the referenced schematic simulations.

2021

Samsung authors report a configurable channel model for DDR4-3DS PHY verification

Samsung Semiconductor India authors report an in-house parameterized channel model integrated into a DDR-PHY verification environment for DDR4-3DS memory. The model injects routing and board delays, skew, crosstalk distortion, duty-cycle variation, setup and hold stress, and glitches; the paper says it enabled RTL-level training-algorithm checks and led to RTL and specification updates in reported cases.

Sep 1, 2020

Scientific Analog announces an SNU/Samsung NAND-sensing SystemVerilog modeling paper

Scientific Analog announces acceptance at ICCAD 2020 of Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations, identifying researchers affiliated with Seoul National University and Samsung. The announcement describes SystemVerilog/XMODEL models tracking cell threshold voltages while exercising read, program and erase algorithms. It reports a 40-microsecond incremental-step-pulse-programming simulation of a 12-Kb single-level-cell block in under two minutes, without specifying the host setup. September 1 is the announcement date; a November 3 conference presentation was planned. Full paper access was unavailable in this check, so author details, silicon correlation and broader performance are not asserted. Scientific Analog is the announcing tool vendor, not an identified research-author affiliation.