Samsung authors present SystemVerilog EEnet models for PMIC loading verification
At DAC 2024, Samsung authors presented a digital mixed-signal verification approach that combines lower-level behavioral models with a SystemVerilog user-defined EEnet to represent electrical loading in power-management IC verification. The presentation describes extending the DMS verification checklist to performance and loading behaviors beyond voltage-only interfaces.
Evidence
Accelerating PMIC Verification Using Digital Mixed Signal Methodology ↗
The official DAC 2024 schedule identifies Samsung authors including Vijay Kumar, dates the presentation to June 24, and describes its SystemVerilog UDT/EEnet PMIC focus.