Samsung authors report configurable AFE/channel models for PCIe receiver-logic verification

Samsung authors present a configurable analog front-end behavioral and channel model in a UVM testbench for 16.0-GT/s PCIe receiver digital logic. Randomizable offsets and FIR channel coefficients exercise eye monitoring, offset calibration, DFE adaptation and margin logic, including deliberately out-of-range conditions that expose retry and timeout bugs. For the reported regression, time to 100% digital code coverage falls from 54.26 to 16.13 hours. The conventional comparison uses an XMODEL analog behavioral model; this does not establish Scientific Analog coauthorship or collaboration. The authors retain conventional circuit-reflecting models for verification requiring actual AFE/channel behavior.