Jaeha Kim explains structural and functional SystemVerilog model generation using a pipelined ADC
In an IEEE Silicon Valley SSCS-sponsored webinar, Jaeha Kim explains automatic SystemVerilog model extraction using a pipelined ADC example. Structural modeling maps circuit devices and connectivity into models, retaining a low abstraction level that limits speed improvement. Functional modeling maps selected circuit regions to predefined templates and requires manual input. The resource record lists a recording and slides. This is a demonstrated modeling workflow, not evidence of fully automatic abstraction of arbitrary analog circuits or deployment at a named customer.
Evidence
Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example — webinar record ↗
The September 15 record describes both approaches, their abstraction/manual-input tradeoffs and recording resources.
Scientific Analog announcement of the IEEE SSCS webinar ↗
The September 3 announcement names IEEE Silicon Valley SSCS sponsorship and the September 15 event time, distinguishing news from presentation.