Jaeha Kim

5 indexed events

Public technical and organizational events indexed by this site.

2025202320212020–2016

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Jan 21, 2025

Jaeha Kim presents SystemVerilog/XMODEL models of three-channel silicon-photonic WDM links

At ASP-DAC 2025, Jaeha Kim, affiliated with Seoul National University and Scientific Analog, presents an invited paper on SystemVerilog/XMODEL simulation of silicon-photonic systems. The conference abstract describes mapping photonic elements to equivalent multi-port transmission lines and event-driven simulation of 5-Gb/s, three-channel WDM links using micro-ring, Mach-Zehnder and electro-absorption modulators. It reports 4.2, 8.3 and 8.3 simulated symbols per second for those examples. These are model-simulation results, not measured link throughput or demonstrated silicon correlation. January 21 is the scheduled presentation date; the publisher proceedings date is later.

Jun 29, 2023

Jaeha Kim presents interacting electrical and logical UCIe PHY models in SystemVerilog

Scientific Analog hosts Jaeha Kim’s UCIe PHY Modeling and Simulation with XMODEL webinar. The resource page describes SystemVerilog models of PLL, DLL, duty-cycle correction, phase interpolation and transmitter/receiver circuits interacting with logical-layer FSMs. Training examples adjust reference voltages, clock/data timing, lane skew and link data rate using pseudo-random data; FSM coverage can be inspected in SystemVerilog. The materials include a recording, slides and a model package. The stated 4–32-GT/s range concerns model/design requirements, not a measured silicon implementation or UCIe compliance certification.

Feb 28, 2023

Jaeha Kim presents reactive UVM measurement of modeled receiver jitter tolerance

Jaeha Kim presents a reactive UVM testbench for high-speed wireline receiver jitter tolerance at DVCon U.S. 2023. The slides identify Seoul National University and Scientific Analog affiliations and place the SystemVerilog/XMODEL transceiver, jitter stimulus and statistical BER instrumentation inside a fixture. Standard UVM components use prior BER results to select the next sinusoidal-jitter amplitude, with linear and binary searches for the pass/fail boundary. The example reports 106 trials at 20 jitter frequencies in 41 minutes for a target BER below 10^-12. The BER comes from statistical model instrumentation, not a measured silicon run or counting 10^12 received bits.

Sep 15, 2021

Jaeha Kim explains structural and functional SystemVerilog model generation using a pipelined ADC

In an IEEE Silicon Valley SSCS-sponsored webinar, Jaeha Kim explains automatic SystemVerilog model extraction using a pipelined ADC example. Structural modeling maps circuit devices and connectivity into models, retaining a low abstraction level that limits speed improvement. Functional modeling maps selected circuit regions to predefined templates and requires manual input. The resource record lists a recording and slides. This is a demonstrated modeling workflow, not evidence of fully automatic abstraction of arbitrary analog circuits or deployment at a named customer.

Aug 8, 2016

Scientific Analog reports SNU/IDEC analog-cell library distribution with XMODEL PLL verification

Scientific Analog reports an August 8, 2016 announcement by Seoul National University’s MICS Group of an Analog Cell Library and reference flow released through IDEC. The flow uses XMODEL for PLL behavior/performance simulation and Synopsys IC Compiler for physical implementation. The reported Samsung 65-nm library supports an 8-GHz LC-oscillator PLL or 1–2-GHz ring-oscillator PLL and is restricted to research groups with appropriate technology access and NDA. The October 4 report quotes MICS director and Scientific Analog founder Jaeha Kim. SNU/IDEC are the library’s releasing/distributing organizations; the named tool vendors and technology provider are not thereby coauthors of every design. The source does not establish unrestricted public library availability.