Jaeha Kim presents interacting electrical and logical UCIe PHY models in SystemVerilog

Scientific Analog hosts Jaeha Kim’s UCIe PHY Modeling and Simulation with XMODEL webinar. The resource page describes SystemVerilog models of PLL, DLL, duty-cycle correction, phase interpolation and transmitter/receiver circuits interacting with logical-layer FSMs. Training examples adjust reference voltages, clock/data timing, lane skew and link data rate using pseudo-random data; FSM coverage can be inspected in SystemVerilog. The materials include a recording, slides and a model package. The stated 4–32-GT/s range concerns model/design requirements, not a measured silicon implementation or UCIe compliance certification.