Siemens author demonstrates capacitance-aware resolved nets and SV-RNM model debugging

A DVCon U.S. 2022 paper by Siemens EDA's Mariam Maurice describes a SystemVerilog resolved-net model carrying voltage, previous voltage, current, capacitance, and resistance. It illustrates loading and filtering effects, real/logic boundary conversion, and interconnect debugging, with ADC, DAC, LDO, and image-sensor examples. The paper identifies UVM, assertions, and functional coverage as future verification work.