Siemens and Ain Shams authors compare a SystemVerilog PLL model with transistor-level outputs
Mariam Maurice, Mohamed Dessouky, and Ashraf Salem published an IEEE Access paper on analog PLL modeling in an event-driven simulator. It uses piecewise-linear value/slope representations with SystemVerilog user-defined types and nets for higher-order loop filters, models fractional division and phase noise, and represents output loading with resolved nets. The paper compares modeled PLL outputs with transistor-level simulation.
Evidence
Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator — full text ↗
The public full text identifies Siemens and Ain Shams affiliations, DOI 10.1109/ACCESS.2023.3299227, the PLL modeling and comparison methods, and a July 26, 2023 publication date. The paper's dated first page takes precedence over the page's generic January 2023 label.