Mariam Maurice presents UVM, assertions, and coverage for ADC/DAC real-number models
At DVCon U.S., Siemens EDA's Mariam Maurice presented methods for verifying ADC and DAC real-number models with randomized stimulus, functional coverage, assertions, and UVM. The paper includes constrained variation of reference and supply voltages and coverage of real-valued signal ranges. Its verification targets are modeled analog devices and their specified behavior.
Evidence
DVCon U.S. session 1049: Functional Verification of Analog Devices modeled using SV-RNM ↗
The official session record identifies Mariam Maurice, Siemens EDA, and the March 6, 2024 presentation.
Functional Verification of Analog Devices modeled using SV-RNM — paper ↗
The conference paper details ADC/DAC RNM verification with constrained random stimulus, voltage-range coverage, assertions, and UVM, including reference and supply variation examples.