SiTime lists a January 2027 Co-op for mixed-signal PLL verification
On October 5, SiTime listed an Ottawa ASIC Digital Verification Co-op for sixteen weeks beginning in January 2027. The student role contributes to mixed-signal PLL IC development by learning the verification environment and testbench and writing test cases for ongoing projects. Verilog, SystemVerilog, UVM, Python and Tcl knowledge are welcomed. The posting does not explicitly assign RNM model development to the Co-op.
Evidence
SiTime: ASIC digital-verification Co-op — employer LinkedIn posting ↗
Employer posting checked October 5, 2026; first publication is not established. It explicitly identifies mixed-signal PLL ICs and a sixteen-week Co-op starting January 2027, with testbench/test-case work and welcomed SystemVerilog/UVM skills.