SiTime

Last researched 2026-10-054 indexed events

Public events shown here describe observable source material, not total internal activity.

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Oct 5, 2026

SiTime lists a January 2027 Co-op for mixed-signal PLL verification

On October 5, SiTime listed an Ottawa ASIC Digital Verification Co-op for sixteen weeks beginning in January 2027. The student role contributes to mixed-signal PLL IC development by learning the verification environment and testbench and writing test cases for ongoing projects. Verilog, SystemVerilog, UVM, Python and Tcl knowledge are welcomed. The posting does not explicitly assign RNM model development to the Co-op.

Jul 18, 2025

SiTime lists SV-RNM verification roles spanning UVM, assertions, coverage, and digital-top sign-off

SiTime posted a verification role whose responsibilities included developing SystemVerilog real-number models, a digital-top SystemVerilog verification plan, UVM scoreboards, monitors, and sequencers, SVA, functional coverage, simulation debug, and tape-out sign-off. The listing named wreal/V-AMS, UVM-AMS, and formal property verification as relevant experience. A Munich listing checked in September 2026 repeats this responsibility and qualification pattern.

Apr 4, 2024

SiTime customer session reports AFS, Symphony, and Solido use for MEMS oscillator SoC verification

At Siemens User2User North America 2024, a customer-presented SiTime session described using Analog FastSPICE, Symphony, and Solido Design Environment to integrate analog and digital components and accelerate verification of high-precision MEMS-based oscillator SoCs.

Jul 2023

Keiichi Kajino's profile dates his SiTime verification-manager role to July 2023

Keiichi Kajino's public professional profile dates the start of his SiTime Manager of Verification role to July 2023 and identifies him as Manager, Japan Verification. His profile separately describes mixed-signal verification experience including mixed-mode simulation, analog and digital assertions, Verilog-A/Verilog-AMS, SystemVerilog RNM, and UVM-based mixed-signal testbenches.