Sony reports SystemVerilog RNM verification for CIS analog/digital specification consistency
A Sony Semiconductor Solutions DVCon Japan presentation reports a CIS verification flow that models analog circuits as SystemVerilog Real Number Models to check analog/digital specification consistency early. The presentation reports a 3000x speedup compared with conventional SPICE and logic-simulator co-simulation.
Evidence
DVCon Japan 2022 Conference Proceedings ↗
Official proceedings for the June 23, 2022 conference, including Sony's CIS SystemVerilog RNM flow and its reported 3000x speedup over SPICE and logic-simulator co-simulation.