STMicroelectronics intern reports SV-UVM LDO verification from its Greater Noida TDP team

A paper by Subhranshu Shekhar Padhee and Thapar’s Anil Arora reports LDO functional verification with a self-checking SystemVerilog/UVM testbench, Cadence Incisive and Synopsys VCS, including code, functional and cross coverage. The author biography identifies Padhee as an intern in STMicroelectronics’ Greater Noida Technology Designing Platform team working on analog and mixed-signal IP verification. This records the published internship-related technical work and contemporaneous company affiliation, not a current organization chart or adoption of the later UVM-MS standard.