STMicroelectronics

Last researched 2026-10-066 indexed events

Public events shown here describe observable source material, not total internal activity.

202620252020–2012

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Sep 2, 2026

STMicroelectronics authors present DMS power estimation and feedforward PLL behavioral modeling

The DVCon India 2026 Day 2 agenda lists two AMS & Low Power Design presentations co-authored by Amit Singh: “Left-Shift Power Estimation in SoC Design: Verification-Integrated Framework for Early Power Estimation Using Digital Mixed-Signal Simulation” with Isha Sharma, and “Design-Focused Feedforward Behavioural Modeling of PLL IPs for Fast SoC Verification” with Preeti Shukla. Public profiles identify Sharma and Shukla with STMicroelectronics. This Event records the two public technical disclosures without asserting unexposed accuracy, runtime, or deployment results.

Feb 16, 2026

STMicroelectronics posts a student role for PMIC top-level verification and analog behavioral models

STMicroelectronics posted a Master Thesis / Working Student Mixed-Signal Modelling and Design Verification role in Munich. The Power Management IC Design Verification Team assigns IC top-level verification, verification-flow development and analog behavioral models, with IEEE/Accellera standards and EDA reference flows. The qualifications include Verilog/SystemVerilog, Python, analog circuits and Cadence flows, with Virtuoso SKILL as a plus. The official JobPosting metadata identifies February 16 as datePosted for job 10540; the role does not identify a particular RNM implementation or a completed automation result.

Oct 15, 2025

ST authors report voltage-aware RNM and UPF verification of an SRAM subsystem

An STMicroelectronics DVCon Europe 2025 paper reports a voltage-aware SRAM verification flow using SystemVerilog real-valued supply modeling and UPF supply-net types for retention memory and bias-generator behavior. For the presented case, the paper contrasts roughly two to three hours of SPICE simulation with 10 to 12 seconds in the digital flow. It also states limitations including PVT representation and simulator-specific UPF behavior.

May 30, 2019

STMicroelectronics intern reports SV-UVM LDO verification from its Greater Noida TDP team

A paper by Subhranshu Shekhar Padhee and Thapar’s Anil Arora reports LDO functional verification with a self-checking SystemVerilog/UVM testbench, Cadence Incisive and Synopsys VCS, including code, functional and cross coverage. The author biography identifies Padhee as an intern in STMicroelectronics’ Greater Noida Technology Designing Platform team working on analog and mixed-signal IP verification. This records the published internship-related technical work and contemporaneous company affiliation, not a current organization chart or adoption of the later UVM-MS standard.

2014

STMicroelectronics and Mentor authors report equivalence validation of analog behavioral models

A DVCon 2014 paper by STMicroelectronics and Mentor Graphics authors describes a verification-plan-driven equivalence-validation component that applies common tests to analog implementations and behavioral models, produces pass/fail results and waivers, and can be reused across projects. The paper reports use by ST's high-speed serial-links group across HDMI, USB, and D-PHY work and says it exposed functional, connectivity, and test-mode differences before models were delivered to SoC teams.

Jun 5, 2012

STMicroelectronics presentation covers metric-driven analog/mixed-signal IP verification

Cadence’s account of DAC 2012 identifies STMicroelectronics’ Pierluigi Daglio and Marco Carlini as authors of “Metric Driven Verification Approach for Analog/Mixed Signal IPs.” The account dates the presentation at the EDA360 Theater in San Francisco to June 5 at 4 p.m. The account was published on August 27, 2012.